In computing systems there is often a need for a "Read and Reset" type register. This is a storage facility that captures the occurrence of and holds events on its input. When the register is read out it is then reset back to a state indicating that the data event has not yet occurred. One usage of a read and reset register is in the detection of error states in a circuit. Here when an error state is entered, the read and reset register is set, and the error processing system is notified. The read and reset register will stay set until after the error processor has read out the value of the register. After the register is read, it is reset by circuitry which detects the action of the error processor reading the register. When the system causing the data events and the system reading the register are asynchronous to each other, a problem arises in the design of the read and reset register.
It is crucial that there does not exist a window of time between when the read and reset register is read out and when the register is reset. Such a window allows for lost data because if the event being captured occurs between the reading of the register and the clearing of the register, the register will not remain in a state indicating the event has occurred.
In IBM Technical Disclosure Bulletin, Vol. 32, No. 5A of October, 1989, pp. 214-216, entitled "Foolproof Event-Catching Register Circuit", of R. W. Voorhees, the window is prevented by relying on the register never being read and reset unless it has been already set.
In IBM Technical Disclosure Bulletin, Vol. 32, No. 6B of November, 1989, pp. 217-218, entitled "Set/Reset System With Slow Set and Fast Reset", of J. L. Le Pennec et al., the window is prevented from occurring by relying on the data event being much longer than the reset pulse. This occurs because often the clock frequencies for the data event and the reset pulse from the reading device differ greatly. This dependency makes this approach unsuitable for many applications.
It is also necessary that if the event occurs during the read action, the register should be set only for that read or only for the next read. Otherwise it would appear that the event occurred twice.